The continued expansion of mobile computing applications requires the packing of ever growing levels of computing power in smaller device footprints. Designers of semiconductor devices are relying on the use of a variety of new chip architectures to meet the new device requirements. These new architectures include flip chip wafer bumping using copper pillars as well as approaches employing through silicon vias (TSV) such as three-dimensional integrated circuits (3D IC) in which wafers are thinned, the resulting dies are stacked and then connected by TSV and 2.5D interposer designs. These approaches pose significant challenges not only for the designers of these new IC architectures, but for the designers of the packaging materials that will be used for these devices.
Often times when constructing these new IC architectures, it becomes necessary to remove two or more polymeric resist layers at the same time. Many times these polymeric layers are composed of materials with vastly different solubility characteristics. A thorough understanding of the characteristics of each polymeric layer is required if removal of both layers is to occur without compromising the integrity of the underlying substrate. Many traditional chemical strippers used in the semiconductor industry are extremely harsh and it is often not possible to use a single stripper to remove all layers without concomitant damage to the underlying substrate. This fact prohibits the use of conventional chemical strippers, and their accompanying processes, in the manufacture of new complex IC architectures. The designers of new advanced materials for semiconductor packaging require strippers that are both potent and selective in their action.
It was unexpectedly discovered that the compositions of this disclosure can remove multiple layers of different dissolution or solubility properties in an organic film on a patterned semiconductor substrate in one step without damaging the substrate or its structure.